From a project flow point of view, an IC review runs very similar to an EOS/ESD troubleshooting project described here.
Pre-tapeout IC reviews focus on risk management by a comprehensive assessment of customers ESD solutions. Besides detecting and eliminating „fatal“ ESD design issues before committing your IC to silicon, such an in-depth review may result in a significant optimization step regarding reliability and even area.
EOS/ESD expert IC reviews include:
- Full IC chip floorplanning including padring, ESD placement, bus architecture and effective bus resistance, RDL wiring, etc).
- Individual IOs or IP macros including ESD integration.
- Individual ESD device architectures or ESD circuits
- Independent assessment if third-party IP is suitable for your IC application
Example padring / bus map from a review project with multiple IO libraries and IP macros for TSMC 40nm. Such an ESD analysis may include the review of library design rules & guidelines, Rbus extraction and cell placement, IP review etc.
A typical delierable is the IC review and optimization report including a padring map with e.g. information on effective bus resistance and potential design rule violations.