TLP and vf-TLP Analysis

This TLP system is an extremely powerful tool. It has been successfully applied for EOS/ESD IC troubleshooting as well as test-strucutre analysis in a wide range of chip applications and technologies.

The most important TLP spec parameters are:

  • TLP current amplitude up to 30A – also sufficient for ultra-high system-level currents
  • Pulse width in multiple steps: 1ns to 1us – from CDM to system-level ESD
  • Pulse rise-times: 100ps to 50ns – for ESD turn-on analysis

The system serves as a regular 100ns-TLP (e.g. for HBM-type analysis), a 2ns-TLP (for CDM-type analysis) as well as a 1us-TLP (e.g. for system-level long-pulse analysis).

Flex-pitch measurement option to apply fast pulses to IC-level (e.g. to IC die)

In particular useful for our ESD IC troubleshooting is a special RF-probe setup, the flex-pitch option. This setup allows us applying fast rise-times on IC-level regardless of the pad spacing in the product, if 200u or 5mm. Using this method, we could for instance determine the response time of potentially slow high-voltage IO ESD protection exposed to IEC GUN stress. In this specific case, we verified that the first fast CDM-like IEC peak caused serious ESD issues due to a quite significant trigger voltage overshoot for one polarity. As a cruccial information for the ESD fix solution, we could rule out that the ESD issue was a result of the voltage built-up in the ESD on-state after protection triggering.

Example TLP data:

1. High-Voltage SCR analysis for 8kV-IEC 41000-4-2 stress for an automotive IO/power applications


2. Analysis of forward turn-on behavior of high-voltage diode with significant trigger voltage overshoot


3. Transient TLP analysis for troubleshooting of non-functional active-clamp design in customer IC


4. Transient TLP analysis of slow low-voltage SCR design in customer IO